Multilevel semiconductor device and structure with oxide bonding

ABSTRACT

A multi-level semiconductor device, the device including: a first level including integrated circuits; a second level including a structure designed to conduct electromagnetic waves, where the second level is disposed above the first level, where the integrated circuits include single crystal transistors; and an oxide layer disposed between the first level and the second level, where the integrated circuits include at least one processor, where the second level is bonded to the oxide layer, and where the bonded includes oxide to oxide bonds.

CROSS-REFERENCE OF RELATED APPLICATION

This application is a continuation-in-part of U.S. patent applicationSer. No. 17/868,776 filed on Jul. 20, 2022; which is acontinuation-in-part of U.S. patent application Ser. No. 17/717,094filed on Apr. 10, 2022, now U.S. Pat. No. 11,437,368 issued on Sep. 6,2022; which is a continuation-in-part of U.S. patent application Ser.No. 17/492,627 filed on Oct. 3, 2021, now U.S. Pat. No. 11,327,227issued on May 10, 2022; which is a continuation-in-part of U.S. patentapplication Ser. No. 17/330,186 filed on May 5, 2021, now U.S. Pat. No.11,163,112 issued on Nov. 2, 2021; which is a continuation-in-part ofU.S. patent application Ser. No. 17/189,201 filed on Mar. 1, 2021, nowU.S. Pat. No. 11,063,071 issued on Julyl 3, 2021; which is acontinuation-in-part of U.S. patent application Ser. No. 17/121,726filed on Dec. 14, 2020, now U.S. Pat. No. 10,978,501 issued on Apr. 13,2021; which is a continuation-in-part of U.S. patent application Ser.No. 17/027,217 filed on Sep. 21, 2020, now U.S. Pat. No. 10,943,934issued on Mar. 9, 2021; which is a continuation-in-part of U.S. patentapplication Ser. No. 16/860,027 filed on Apr. 27, 2020, now U.S. Pat.No. 10,833,108 issued on Nov. 11, 2020; which is a continuation-in-partof U.S. patent application Ser. No. 15/920,499 filed on Mar. 14, 2018,now U.S. Pat. No. 10,679,977 issued on Jun. 9, 2020; which is acontinuation-in-part of U.S. patent application Ser. No. 14/936,657filed on Nov. 9, 2015, now U.S. Pat. No. 9,941,319 issued on Apr. 10,2018; which is a continuation-in-part of U.S. patent application Ser.No. 13/274,161 filed on Oct. 14, 2011, now U.S. Pat. No. 9,197,804issued on Nov. 24, 2015; and this application is a continuation-in-partof U.S. patent application Ser. No. 12/904,103 filed on Oct. 13, 2010,now U.S. Pat. No. 8,163,581 issued on Apr. 24, 2012; the entire contentsof all of the preceding are incorporated herein by reference.

BACKGROUND OF THE INVENTION (A) Field of the Invention

This invention describes applications of monolithic 3D integration tovarious disciplines, including but not limited to, for example,light-emitting diodes, displays, image-sensors and solar cells.

(B) Discussion of Background Art

Semiconductor and optoelectronic devices often require thinmonocrystalline (or single-crystal) films deposited on a certain wafer.To enable this deposition, many techniques, generally referred to aslayer transfer technologies, have been developed. These include:

-   -   Ion-cut, variations of which are referred to as smart-cut,        nano-cleave and smart-cleave: Further information on ion-cut        technology is given in “Frontiers of silicon-on-insulator,” J.        Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S.        Cristolovean (“Celler”) and also in “Mechanically induced Si        layer transfer in hydrogen-implanted Si wafers,” Appl. Phys.        Lett., vol. 76, pp. 2370-2372, 2000 by K. Henttinen, I. Suni,        and S. S. Lau (“Hentinnen”).    -   Porous silicon approaches such as ELTRAN: These are described in        “Eltran, Novel SOI Wafer Technology”, JSAP International, Number        4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”).

Lift-off with a temporary substrate, also referred to as epitaxiallift-off: This is described in “Epitaxial lift-off and itsapplications”, 1993 Semicond. Sci. Technol. 8 1124 by P. Demeester, etal (“Demeester”).

-   -   Bonding a substrate with single crystal layers followed by        Polishing, Time-controlled etch-back or Etch-stop layer        controlled etch-back to thin the bonded substrate: These are        described in U.S. Pat. No. 6,806,171 by A. Ulyashin and A.        Usenko (“Ulyashin”) and “Enabling SOI-Based Assembly Technology        for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM        Tech. Digest, p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L.        Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D.        Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D.        DiMilia, M. T. Robson, E. Duch, M. Farinelli, C. Wang, R. A.        Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T.        Kwietniak, C. D′Emic, J. Ott, A. M. Young, K. W. Guarini, and M.        Ieong (“Topol”).    -   Bonding a wafer with a Gallium Nitride film epitaxially grown on        a sapphire substrate followed by laser lift-off for removing the        transparent sapphire substrate: This method may be suitable for        deposition of Gallium Nitride thin films, and is described in        U.S. Pat. No. 6,071,795 by Nathan W. Cheung, Timothy D. Sands        and William S. Wong (“Cheung”).    -   Rubber stamp layer transfer: This is described in “Solar cells        sliced and diced”, 19th May 2010, Nature News.        With novel applications of these methods and recognition of        their individual strengths and weaknesses, one can significantly        enhance today's light-emitting diode (LED), display,        image-sensor and solar cell technologies.

Background on LEDs

Light emitting diodes (LEDs) are used in many applications, includingautomotive lighting, incandescent bulb replacements, and as backlightsfor displays. Red LEDs are typically made on Gallium Arsenide (GaAs)substrates, and include quantum wells constructed of various materialssuch as AlInGaP and GaInP. Blue and green LEDs are typically made onSapphire or Silicon Carbide (SiC) or bulk Gallium Nitride (GaN)substrates, and include quantum wells constructed of various materialssuch as GaN and InGaN.

A white LED for lighting and display applications can be constructed byeither using a blue LED coated with phosphor (called phosphor-coated LEDor pcLED) or by combining light from red, blue, and green LEDs (calledRGB LED). RGB LEDs are typically constructed by placing red, blue, andgreen LEDs side-by-side. While RGB LEDs are more energy-efficient thanpcLEDs, they are less efficient in mixing red, blue and green colors toform white light. They also are much more costly than pcLEDs. To tackleissues with RGB LEDs, several proposals have been made.

One RGB LED proposal from Hong Kong University is described in “Designof vertically stacked polychromatic light emitting diodes”, OpticsExpress, June 2009 by K. Hui, X. Wang, et al (“Hui”). It involvesstacking red, blue, and green LEDs on top of each other afterindividually packaging each of these LEDs. While this solves lightmixing problems, this RGB-LED is still much more costly than a pcLEDsolution since three LEDs for red, blue, and green color need to bepackaged. A pcLED, on the other hand, requires just one LED to bepackaged and coated with phosphor.

Another RGB LED proposal from Nichia Corporation is described in“Phosphor Free High-Luminous-Efficiency White Light-Emitting DiodesComposed of InGaN Multi-Quantum Well”, Japanese Journal of AppliedPhysics, 2002 by M. Yamada, Y. Narukawa, et al. (“Yamada”). It involvesconstructing and stacking red, blue and green LEDs of GaN-basedmaterials on a sapphire or SiC substrate. However, red LEDs are notefficient when constructed with GaN-based material systems, and thathampers usefulness of this implementation. It is not possible to depositdefect-free AlInGaP/InGaP for red LEDs on the same substrate as GaNbased blue and green LEDs, due to a mismatch in thermal expansionco-efficient between the various material systems.

Yet another RGB-LED proposal is described in “Cascade Single chipphosphor-free while light emitting diodes”, Applied Physics Letters,2008 by X. Guo, G. Shen, et al. (“Guo”). It involves bonding GaAs basedred LEDs with GaN based blue-green LEDs to produce white light.

Unfortunately, this bonding process requires 600° C. temperatures,causing issues with mismatch of thermal expansion co-efficients andcracking. Another publication on this topic is “A trichromaticphosphor-free white light-emitting diode by using adhesive bondingscheme”, Proc. SPIE, Vol. 7635, 2009 by D. Chuai, X. Guo, et al.(“Chuai”). It involves bonding red LEDs with green-blue LED stacks.Bonding is done at the die level after dicing, which is more costly thana wafer-based approach.

U.S. patent application Ser. No. 12/130,824 describes various stackedRGB LED devices. It also briefly mentions a method for construction of astacked LED where all layers of the stacked LED are transferred usinglift-off with a temporary carrier and Indium Tin Oxide (ITO) tosemiconductor bonding. This method has several issues for constructing aRGB LED stack. First, it is difficult to manufacture a lift-off with atemporary carrier of red LEDs for producing a RGB LED stack, especiallyfor substrates larger than 2 inch. This is because red LEDs aretypically constructed on non-transparent GaAs substrates, and lift-offwith a temporary carrier is done by using an epitaxial lift-off process.Here, the thin film to be transferred typically sits atop a“release-layer” (eg. AlAs), this release layer is removed by etchprocedures after the thin film is attached to a temporary substrate.Scaling this process to 4 inch wafers and bigger is difficult. Second,it is very difficult to perform the bonding of ITO to semiconductormaterials of a LED layer at reasonable temperatures, as described in thepatent application Ser. No. 12/130,824.

It is therefore clear that a better method for constructing RGB LEDswill be helpful. Since RGB LEDs are significantly more efficient thanpcLEDs, they can be used as replacements of today's phosphor-based LEDsfor many applications, provided a cheap and effective method ofconstructing RGB LEDs can be invented.

Background on Image-sensors:

Image sensors are used in applications such as cameras. Red, blue, andgreen components of the incident light are sensed and stored in digitalformat. CMOS image sensors typically contain a photodetector and sensingcircuitry. Almost all image sensors today have both the photodetectorand sensing circuitry on the same chip. Since the area consumed by thesensing circuits is high, the photodetector cannot see the entireincident light, and image capture is not as efficient.

To tackle this problem, several researchers have proposed building thephotodetectors and the sensing circuitry on separate chips and stackingthem on top of each other. A publication that describes this method is“Megapixel CMOS image sensor fabricated in three-dimensional integratedcircuit technology”, Intl. Solid State Circuits Conference 2005 bySuntharalingam, V., Berger, R., et al. (“Suntharalingam”). Theseproposals use through-silicon via (TSV) technology where alignment isdone in conjunction with bonding. However, pixel size is reaching the 1μm range, and successfully processing TSVs in the 1 μm range or below isvery difficult. This is due to alignment issues while bonding. Forexample, the International Technology Roadmap for Semiconductors (ITRS)suggests that the 2-4 μm TSV pitch will be the industry standard until2012. A 2-4 μm pitch TSV will be too big for a sub-1 μm pixel.Therefore, novel techniques of stacking photodetectors and sensingcircuitry are required.

A possible solution to this problem is given in “Setting up 3DSequential Integration for Back-Illuminated CMOS Image Sensors withHighly Miniaturized Pixels with Low Temperature Fully-depleted SOITransistors,” IEDM, p.1-4 (2008) by P. Coudrain et al. (“Coudrain”). Inthe publication, transistors are monolithically integrated on top ofphotodetectors. Unfortunately, transistor process temperatures reach600° C. or more. This is not ideal for transistors (that require ahigher thermal budget) and photodetectors (that may prefer a lowerthermal budget).

Background on Displays:

Liquid Crystal Displays (LCDs) can be classified into two types based onmanufacturing technology utilized: (1) Large-size displays that are madeof amorphous/polycrystalline silicon thin-film-transistors (TFTs), and(2) Microdisplays that utilize single-crystal silicon transistors.Microdisplays are typically used where very high resolution is needed,such as camera/camcorder view-finders, projectors and wearablecomputers.

Microdisplays are made in semiconductor fabs with 200 mm or 300 mmwafers. They are typically constructed with LCOS(Liquid-Crystal-on-Silicon) Technology and are reflective in nature. Anexception to this trend of reflective microdisplays is technology fromKopin Corporation (U.S. Pat. No. 5,317,236, filed December 1991). Thiscompany utilizes transmittive displays with a lift-off layer transferscheme. Transmittive displays may be generally preferred for variousapplications.

While lift-off layer transfer schemes are viable for transmittivedisplays, they are frequently not used for semiconductor manufacturingdue to yield issues. Therefore, other layer transfer schemes will behelpful. However, it is not easy to utilize other layer transfer schemesfor making transistors in microdisplays. For example, application of“smart-cut” layer transfer to attach monocrystalline silicon transistorsto glass is described in “Integration of Single Crystal Si TFTs andCircuits on a Large Glass Substrate”, IEDM 2009 by Y. Takafuji, Y.Fukushima, K. Tomiyasu, et al. (“Takafuji”). Unfortunately, hydrogen isimplanted through the gate oxide of transferred transistors in theprocess, and this degrades performance. Process temperatures are as highas 600° C. in this paper, and this requires costly glass substrates.Several challenges therefore need to be overcome for efficient layertransfer, and require innovation.

Background on Solar Cells:

Solar cells can be constructed of several materials such as, forexample, silicon and compound semiconductors. The highest efficiencysolar cells are typically multi junction solar cells that areconstructed of compound semiconductor materials. These multi junctionsolar cells are typically constructed on a germanium substrate, andsemiconductors with various band-gaps are epitaxially grown atop thissubstrate to capture different portions of the solar spectrum.

There are a few issues with standard multi junction solar cells. Sincemultiple junctions are grown epitaxially above a single substrate (suchas Germanium) at high temperature, materials used for differentjunctions are restricted to those that have lattice constants andthermal expansion co-efficients close to those of the substrate.Therefore, the choice of materials used to build junctions for multijunction solar cells is limited. As a result, most multi junction solarcells commercially available today cannot capture the full solarspectrum. Efficiency of the solar cell can be improved if a large bandof the solar spectrum is captured. Furthermore, multi junction solarcells today suffer from high cost of the substrate above which multiplejunctions are epitaxially grown. Methods to build multi junction solarcells that tackle both these issues will be helpful.

A method of making multi junction solar cells by mechanically bondingtwo solar cells, one with a Germanium junction and another with acompound semiconductor junction is described in “Towards highlyefficient 4-terminal mechanical photovoltaic stacks”, III-Vs Review,Volume 19, Issue 7, September-October 2006 by Giovanni Flamand, JefPoortmans (“Flamand”). In this work, the authors make the compoundsemiconductor junctions on a Germanium substrate epitaxially. They thenetch away the entire Germanium substrate after bonding to the othersubstrate with the Germanium junction. The process uses two Germaniumsubstrates, and is therefore expensive.

Techniques to create multi junction solar cells with layer transfer havebeen described in “Wafer bonding and layer transfer processes for4-junction high efficiency solar cells,” Photovoltaic SpecialistsConference, 2002. Conference Record of the Twenty Ninth IEEE, vol., no.,pp. 1039-1042, 19-24 May 2002 by Zahler, J. M.; Fontcuberta i Morral,A.; Chang-Geun Ahn; Atwater, H. A.; Wanlass, M. W.; Chu, C. and Iles, P.A. An anneal is used for ion-cut purposes, and this anneal is typicallydone at temperatures higher than 350-400° C. (if high bond strength isdesired). When that happens, cracking and defects can be produced due tomismatch of co-efficients of thermal expansion between various layers inthe stack. Furthermore, semiconductor layers are bonded together, andthe quality of this bond not as good as oxide-to-oxide bonding,especially for lower process temperatures.

Background on CCD Sensors:

Image sensors based on Charge-Coupled Device (CCD) technology has beenaround for several decades. The CCD technology relies on a collect andshift scheme, wherein charges are collected in individual cellsaccording to the luminosity of the light falling on each of them, thenthe charges are sequentially shifted towards one edge of the sensorwhere readout circuits read the sequence of charges one at a time.

The advantage of CCD technology is it has better light sensitivity sincealmost the entire CCD cell area is dedicated to light collecting, andthe control and readout circuits are all on one edge not blocking thelight. On the other hand, in a CMOS sensor, the photodiodes in each cellhave to share space with the control and readout circuits adjacent tothem, and so their size and light sensitivity are therefore limited.

The main issue with CCD technology is this sequential shifting of imageinformation from cell to cell is slow and limits the speed and celldensity of CCD image sensors. A potential solution is to put the readoutcircuits directly under each CCD cell, so that the information is readin parallel rather than in time sequence, thus removing the shiftingdelay entirely.

Background on High Dynamic Range (HDR) Sensors:

Ever since the advent of commercial digital photography in the 1990s,achieving High Dynamic Range (HDR) imaging has been a goal for mostcamera manufacturers in their image sensors. The idea is to use varioustechniques to compensate for the lower dynamic range of image sensorsrelative to the human eye. The concept of HDR however, is not new.Combining multiple exposures of a single image to achieve a wide rangeof luminosity was actually pioneered in the 1850s by Gustave Le Gray torender seascapes showing both the bright sky and the dark sea. This wasnecessary to produce realistic photographic images as the film used atthat time had exptremely low dynamic range compared to the human eye.

In digital cameras, the typical approach is to capture images usingexposure bracketing, and then combining them into a single HDR image.The issue with this is that multiple exposures are performed over someperiod of time, and if there is movement of the camera or target duringthe time of the exposures, the final HDR image will reflect this by lossof sharpness. Moreover, multiple images may lead to large data instorage devices. Other methods use software algorithms to extract HDRinformation from a single exposure, but as they can only processinformation that is recordable by the sensor, there is a permanent lossof some details.

Over the past 40 years, there has been a dramatic increase infunctionality and performance of Integrated Circuits (ICs). This haslargely been due to the phenomenon of “scaling”; i.e., component sizeswithin ICs have been reduced (“scaled”) with every successive generationof technology. There are two main classes of components in ComplementaryMetal Oxide Semiconductor (CMOS) ICs, namely transistors and wires. With“scaling”, transistor performance and density typically improve and thishas contributed to the previously-mentioned increases in IC performanceand functionality. However, wires (interconnects) that connect togethertransistors degrade in performance with “scaling”. The situation todayis that wires dominate the performance, functionality and powerconsumption of ICs.

3D stacking of semiconductor devices or chips is one avenue to tacklethe wire issues. By arranging transistors in 3 dimensions instead of 2dimensions (as was the case in the 1990s), the transistors in ICs can beplaced closer to each other. This reduces wire lengths and keeps wiringdelay low.

There are many techniques to construct 3D stacked integrated circuits orchips including:

Through-silicon via (TSV) technology: Multiple layers of transistors(with or without wiring levels) can be constructed separately. Followingthis, they can be bonded to each other and connected to each other withthrough-silicon vias (TSVs).

Monolithic 3D technology: With this approach, multiple layers oftransistors and wires can be monolithically constructed. Some monolithic3D and 3DIC approaches are described in U.S. Pat. Nos. 8,273,610,8,298,875, 8,362,482, 8,378,715, 8,379,458, 8,450,804, 8,557,632,8,574,929, 8,581,349, 8,642,416, 8,669,778, 8,674,470, 8,687,399,8,742,476, 8,803,206, 8,836,073, 8,902,663, 8,994,404, 9,023,688,9,029,173, 9,030,858, 9,117,749, 9,142,553, 9,219,005, 9,385,058,9,406,670, 9,460,978, 9,509,313, 9,640,531, 9,691,760, 9,711,407,9,721,927, 9,799,761, 9,871,034, 9,953,870, 9,953,994, 10,014,292,10,014,318, 10,515,981, 10,892,016, 10,991,675, 11,121,121, 11,502,095,10,892,016, 11,270,988; and pending U.S. Patent Application Publicationsand applications, 14/642,724, 15/150,395, 15/173,686, 62/651,722;62/681,249, 62/713,345, 62/770,751, 62/952,222, 62/824,288, 63/075,067,63/091,307, 63/115,000, 63/220,443, 2021/0242189, 2020/0013791; and PCTApplications (and Publications): PCT/US2010/052093, PCT/US2011/042071(WO2012/015550), PCT/US2016/52726 (WO2017053329), PCT/US2017/052359(WO2018/071143), PCT/US2018/016759 (WO2018144957), PCT/US2018/52332(WO2019/060798), PCT/US2021/44110, and PCT/US22/44165. The entire contentsof all of the foregoing patents, publications, and applications areincorporated herein by reference.

Electro-Optics: There is also work done for integrated monolithic 3Dincluding layers of different crystals, such as U.S. Pat. Nos.8,283,215, 8,163,581, 8,753,913, 8,823,122, 9,197,804, 9,419,031,9,941,319, 10,679,977, 10,943,934, 10,998,374, 11,063,071, and11,133,344. The entire contents of all of the foregoing patents areincorporated herein by reference.

In addition, the entire contents of U.S. Pat. Nos. 8,273,610, 9,000,557,8,753,913, 8,823,122, 9,419,031, 9,197,804, 9,941,319, 10,679,977,10,833,108, 10,943,934, 10,978,501, 10,998,374, 11,063,071, 11,133,344,11,163,112, 11,164,898, 11,315,965, 11,327,227 and U.S. PatentApplication Publication 2020/0194416, and U.S. patent application Ser.No. 17/402,527; are incorporated herein by reference.

SUMMARY

Techniques to utilize layer transfer schemes such as ion-cut to formnovel light emitting diodes (LEDs), CMOS image sensors, displays,microdisplays and solar cells are discussed.

In one aspect, a multi-level semiconductor device, the device including:a first level including integrated circuits; a second level including anoptical waveguide, where the second level is disposed above the firstlevel, where the first level includes crystalline silicon; and an oxidelayer disposed between the first level and the second level, where thesecond level is bonded to the oxide layer, and where the bonded includesoxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including an optical waveguide; a second levelincluding integrated circuits, where the second level is disposed abovethe first level, where the first level includes crystalline silicon; andan oxide layer disposed between the first level and the second level,where the second level is bonded to the oxide layer, and where thebonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a plurality of optical modulators, where the second level isdisposed above the first level, where the first level includescrystalline silicon; and an oxide layer disposed between the first leveland the second level, where the second level is bonded to the oxidelayer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding an electromagnetic waveguide, where the second level isdisposed above the first level, where the first level includescrystalline silicon; and an oxide layer disposed between the first leveland the second level, where the second level is bonded to the oxidelayer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including an electromagnetic waveguide; asecond level including integrated circuits, where the second level isdisposed above the first level, where the first level includescrystalline silicon; and an oxide layer disposed between the first leveland the second level, where the second level is bonded to the oxidelayer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a plurality of electromagnetic modulators, where the secondlevel is disposed above the first level, where the first level includescrystalline silicon; and an oxide layer disposed between the first leveland the second level, where the second level is bonded to the oxidelayer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a structure designed to conduct electromagnetic waves in aconfined manner, where the second level is disposed above the firstlevel, where the first level includes crystalline silicon, where thesecond level includes crystalline silicon; and an oxide layer disposedbetween the first level and the second level, where the second level isbonded to the oxide layer, and where the bonded includes oxide to oxidebonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including a structure designed to conductelectromagnetic waves in a confined manner; a second level includingintegrated circuits, where the second level is disposed above the firstlevel, where the first level includes crystalline silicon; and an oxidelayer disposed between the first level and the second level, where thesecond level is bonded to the oxide layer, and where the bonded includesoxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a plurality of electromagnetic modulators, where the secondlevel is disposed above the first level, where the first level includescrystalline silicon, where the second level includes crystallinesilicon; and an oxide layer disposed between the first level and thesecond level, where the second level is bonded to the first level.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a structure designed to conduct electromagnetic waves, wherethe second level is disposed above the first level, where the firstlevel includes crystalline silicon, where the second level includescrystalline silicon; an oxide layer disposed between the first level andthe second level; and a plurality of electromagnetic modulators, wherethe second level is bonded to the oxide layer, and where the bondedincludes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including a structure designed to conductelectromagnetic waves; a second level including integrated circuits,where the second level is disposed above the first level; a plurality ofelectromagnetic modulators; and an oxide layer disposed between thefirst level and the second level, where the first level includescrystalline silicon, where the second level is bonded to the oxidelayer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits andelectromagnetic modulators; a second level including a plurality oftransistors, where the second level is disposed above the first level,where the first level includes crystalline silicon, where the secondlevel includes crystalline silicon; and an oxide layer disposed betweenthe first level and the second level, where the second level is bondedto the first level.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a structure designed to conduct electromagnetic waves, wherethe second level is disposed above the first level, where the firstlevel includes crystalline silicon; an oxide layer disposed between thefirst level and the second level; and a plurality of electromagneticmodulators, where the second level is bonded to the oxide layer, andwhere the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including a structure designed to conductelectromagnetic waves; a second level including integrated circuits,where the second level is disposed above the first level; a plurality ofelectromagnetic modulators; and an oxide layer disposed between thefirst level and the second level, where the second level is bonded tothe oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits andelectromagnetic modulators; a second level including a plurality ofinterconnects lines, where the second level is disposed above the firstlevel, where the first level includes crystalline silicon; and an oxidelayer disposed between the first level and the second level, where thesecond level is bonded to the first level, and where the bonded includesoxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a structure designed to conduct electromagnetic waves, wherethe second level is disposed above the first level, where the firstlevel includes crystalline silicon; and an oxide layer disposed betweenthe first level and the second level; where the second level is bondedto the oxide layer, and where the bonded includes oxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including a structure designed to conductelectromagnetic waves; a second level including integrated circuits,where the second level is disposed above the first level, and at leastone transmitter and at least one receiver; and an oxide layer disposedbetween the first level and the second level, where the second level isbonded to the oxide layer, and where the bonded includes oxide to oxidebonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits and communicationcontrol circuits; a second level including a plurality of interconnectlines, where the second level is disposed above the first level, wherethe first level includes crystalline silicon; and an oxide layerdisposed between the first level and the second level, where the secondlevel is bonded to the first level, and where the bonded includes oxideto oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a structure designed to conduct electromagnetic waves, wherethe second level is disposed above the first level, where the integratedcircuits include single crystal transistors; and an oxide layer disposedbetween the first level and the second level, where the second level isbonded to the oxide layer, and where the bonded includes oxide to oxidebonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including a structure designed to conductelectromagnetic waves; a second level including integrated circuits,where the second level is disposed above the first level, where theintegrated circuits include single crystal transistors; and an oxidelayer disposed between the first level and the second level, where thesecond level is bonded to the oxide layer, and where the bonded includesoxide to oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits and communicationcontrol circuits; a second level including a plurality of interconnectlines, where the second level is disposed above the first level, wherethe first level includes a crystalline material; an oxide layer disposedbetween the first level and the second level, where the second level isbonded to the first level, where the bonded includes oxide to oxidebonds; and at least one electromagnetic wave receiver.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits; a second levelincluding a structure designed to conduct electromagnetic waves, wherethe second level is disposed above the first level, where the integratedcircuits include single crystal transistors; and an oxide layer disposedbetween the first level and the second level, where the integratedcircuits include at least one processor, where the second level isbonded to the oxide layer, and where the bonded includes oxide to oxidebonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including a structure designed to conductelectromagnetic waves; a second level including integrated circuits,where the second level is disposed above the first level, where theintegrated circuits include single crystal transistors; and an oxidelayer disposed between the first level and the second level, where theintegrated circuits include at least one processor, where the secondlevel is bonded to the oxide layer, and where the bonded includes oxideto oxide bonds.

In another aspect, a multi-level semiconductor device, the deviceincluding: a first level including integrated circuits and communicationcontrol circuits; a second level including a plurality of interconnectlines, where the second level is disposed above the first level, wherethe first level includes a crystalline material; and an oxide layerdisposed between the first level and the second level, where the secondlevel is bonded to the first level, where the bonded includes oxide tooxide bonds; and at least one electromagnetic wave transmitter.

BRIEF DESCRIPTION OF THE DRAWINGS

Various embodiments of the invention will be understood and appreciatedmore fully from the following detailed description, taken in conjunctionwith the drawings in which:

FIGS. 1A-1G are exemplary drawn illustrations of a display constructedusing sub−400° C. processed single crystal silicon recessed channeltransistors on a glass substrate;

FIGS. 2A-2I are exemplary drawn illustrations of a display constructedusing sub−400° C. processed single crystal silicon replacement gatetransistors on a glass substrate;

FIGS. 3A-3F are exemplary drawn illustrations of a display constructedusing sub−400° C. processed single crystal junction-less transistors ona glass substrate;

FIGS. 4A-4D are exemplary drawn illustrations of a display constructedusing sub−400° C. processed amorphous silicon or polysiliconjunctionless transistors on a glass substrate;

FIGS. 5A-5C are exemplary drawn illustrations of a microdisplayconstructed using stacked RGB LEDs and control circuits are connected toeach pixel with solder bumps;

FIGS. 6A-6D are exemplary drawn illustrations of a microdisplayconstructed using stacked RGB LEDs and control circuits aremonolithically stacked above the LED. FIGS. 31A-H illustrate anembodiment of this invention, where a LED-driven chip-to-chip opticalinterconnect is constructed by monolithically stacking using layertransfer techniques;

FIGS. 7A-7H illustrate an embodiment of this invention, where aLED-driven chip-to-chip optical interconnect is constructed bymonolithically stacking using layer transfer techniques;

FIGS. 8A-8D illustrate an embodiment of this invention, where alaser-driven chip-to-chip optical interconnect is constructed bymonolithically stacking using layer transfer techniques;

FIGS. 9A-9C illustrate an embodiment of this invention, where aLED-driven on-chip optical interconnect is constructed by monolithicallystacking using layer transfer techniques;

FIG. 10 illustrates a typical hollow-metal waveguide (HMWG) structurewhich enables on-chip communication via waveguides stacked on top of theactive layer of the chip (prior art); and

FIGS. 11A-11C illustrate an embodiment of this invention, where alaser-driven on-chip optical interconnect is constructed bymonolithically stacking using layer transfer techniques.

DETAILED DESCRIPTION

Embodiments of the present invention are now described with reference toFIGS. 1-11 , it being appreciated that the figures illustrate thesubject matter not to scale or to measure.

A smart layer transfer may be defined as one or more of the followingprocesses:

-   -   Ion-cut, variations of which are referred to as smart-cut,        nano-cleave and smart-cleave: Further information on ion-cut        technology is given in “Frontiers of silicon-on-insulator,” J.        Appl. Phys. 93, 4955-4978 (2003) by G. K. Celler and S.        Cristolovean (“Celler”) and also in “Mechanically induced Si        layer transfer in hydrogen-implanted Si wafers,” Appl. Phys.        Lett., vol. 76, pp. 2370-2372, 2000 by K. Henttinen, I. Suni,        and S. S. Lau (“Hentinnen”).    -   Porous silicon approaches such as ELTRAN: These are described in        “Eltran, Novel SOI Wafer Technology,” JSAP International, Number        4, July 2001 by T. Yonehara and K. Sakaguchi (“Yonehara”).    -   Bonding a substrate with single crystal layers followed by        Polishing, Time-controlled etch-back or Etch-stop layer        controlled etch-back to thin the bonded substrate: These are        described in U.S. Pat. No. 6,806,171 by A. Ulyashin and A.        Usenko (“Ulyashin”) and “Enabling SOI-Based Assembly Technology        for Three-Dimensional (3D) Integrated Circuits (ICs),” IEDM        Tech. Digest, p. 363 (2005) by A. W. Topol, D. C. La Tulipe, L.        Shi, S. M. Alam, D. J. Frank, S. E. Steen, J. Vichiconti, D.        Posillico, M. Cobb, S. Medd, J. Patel, S. Goma, D.        DiMilia, M. T. Robson, E. Duch, M. Farinelli, C. Wang, R. A.        Conti, D. M. Canaperi, L. Deligianni, A. Kumar, K. T.        Kwietniak, C. D′Emic, J. Ott, A. M. Young, K. W. Guarini, and M.        Ieong (“Topol”).    -   Bonding a wafer with a Gallium Nitride film epitaxially grown on        a sapphire substrate followed by laser lift-off for removing the        transparent sapphire substrate: This method may be suitable for        deposition of Gallium Nitride thin films, and is described in        U.S. Pat. No. 6,071,795 by Nathan W. Cheung, Timothy D. Sands        and William S. Wong (“Cheung”).    -   Rubber stamp layer transfer: This is described in “Solar cells        sliced and diced,” 19th May 2010, Nature News.

This process of constructing RGB LEDs could include several steps thatoccur in a sequence from Step (A) to Step (S). Many of them share commoncharacteristics, features, modes of operation, etc. When the samereference numbers are used in different drawing figures, they are usedto indicate analogous, similar or identical structures to enhance theunderstanding of the present invention by clarifying the relationshipsbetween the structures and embodiments presented in the variousdiagrams—particularly in relating analogous, similar or identicalfunctionality to different physical structures.

NuDisplay Technology:

In displays and microdisplays (small size displays where opticalmagnification is needed), transistors need to be formed on glass orplastic substrates. These substrates typically cannot withstand highprocess temperatures (e.g., >400° C.). Layer transfer can beadvantageously used for constructing displays and microdisplays as well,since it may enable transistors to be processed on these substrates at<400° C. Various embodiments of transistors constructed on glasssubstrates are described in this patent application. These transistorsconstructed on glass substrates could form part of liquid crystaldisplays (LCDs) or other types of displays. It will be clear to thoseskilled in the art based on the present disclosure that these techniquescan also be applied to plastic substrates.

FIGS. 1A-1G describe a process for forming recessed channel singlecrystal (or monocrystalline) transistors on glass substrates at atemperature approximately less than 400° C. for display and microdisplayapplications. This process could include several steps that occur in asequence from Step (A) to Step (G). Many of these steps share commoncharacteristics, features, modes of operation, etc. When identicalreference numbers are used in different drawing figures, they are usedto indicate analogous, similar or identical structures to enhance theunderstanding of the present invention by clarifying the relationshipsbetween the structures and embodiments presented in the variousdiagrams—particularly in relating analogous, similar or identicalfunctionality to different physical structures.

Step (A) is illustrated in FIG. 1A. A silicon wafer 2202 is taken and an+ region 2204 is formed by ion implantation. Following this formation,a layer of p- Silicon 2206 is epitaxially grown. An oxide layer 2210 isthen deposited. Following this deposition, an anneal is performed toactivate dopants in various layers. It will be clear to one skilled inthe art based on the present disclosure that various other procedurescan be used to get the structure shown in FIG. 22A.Step (B) is illustrated in FIG. 1B. Hydrogen is implanted into thestructure shown in FIG. 22A at a certain depth indicated by 2212.Alternatively, Helium can be used for this purpose. Various elements inFIG. 1B, such as 2202, 2204, 2006, and 2210 have been describedpreviously.Step (C) is illustrated in FIG. 1C. A glass substrate 2214 is taken anda silicon oxide layer 2216 is deposited atop it at compatibletemperatures.Step (D) is illustrated in FIG. 1D. Various elements in FIG. 1D, such as2202, 2204, 2206, 2210, 2214, and 2216 have been described previously.The structure shown in FIG. 1B is flipped and bonded to the structureshown in FIG. 1C using oxide-to-oxide bonding of layers 2210 and 2216.Step (E) is illustrated in FIG. 1E. The structure shown in FIG. 1D iscleaved at the hydrogen plane 2212 of FIG. 1D. A CMP is then done toplanarize the surface and yield the n+Si layer 2218. Various otherelements in FIG. 1E, such as 2214, 2216, 2210 and 2206 have beendescribed previously.Step (F) is illustrated in FIG. 1F. Various elements in FIG. 1F such as2214, 2216, 2210, and 2206 have been described previously. An oxidelayer 2220 is formed using a shallow trench isolation (STI) process.This helps isolate transistors.

Step (G) is illustrated in FIG. 1G. Various elements in FIG. 1G such as2210, 2216, 2220 and 2214 have been described previously. Using etchtechniques, part of the n+ Silicon layer from FIG. 1F and optionally p-Silicon layer from FIG. 1F are etched. After this a thin gate dielectricis deposited, after which a gate dielectrode is deposited. The gatedielectric and gate electrode are then polished away to form the gatedielectric layer 2224 and gate electrode layer 2222. The n+ Siliconlayers 2228 and 2226 form the source and drain regions of thetransistors while the p- Silicon region after this step is indicated by2230. Contacts and other parts of the display/microdisplay are thenfabricated. It can be observed that during the whole process, the glasssubstrate substantially always experiences temperatures less than 400°C., or even lower. This is because the crystalline silicon can betransferred atop the glass substrate at a temperature less than 400° C.,and dopants are pre-activated before layer transfer to glass.

FIG. 2A-2I describes a process of forming both nMOS and pMOS transistorswith single-crystal silicon on a glass substrate at temperatures lessthan 400° C., and even lower. Ion-cut technology (which is a smart layertransfer technology) is used. While the process flow described is shownfor both nMOS and pMOS on a glass substrate, it could also be used forjust constructing nMOS devices or for just constructing pMOS devices.This process could include several steps that occur in a sequence fromStep (A) to Step (H). Many of these steps share common characteristics,features, modes of operation, etc. When identical reference numbers areused in different drawing figures, they are used to indicate analogous,similar or identical structures to enhance the understanding of thepresent invention by clarifying the relationships between the structuresand embodiments presented in the various diagrams—particularly inrelating analogous, similar or identical functionality to differentphysical structures.

Step (A) is illustrated in FIG. 2A. A p- Silicon wafer 2302 is taken anda n well 2304 is formed on the p- Silicon wafer 2302. Various additionalimplants to optimize dopant profiles can also be done. Following thisformation, an isolation process is conducted to form isolation regions2306. A dummy gate dielectric 2310 made of silicon dioxide and a dummygate electrode 2308 made of polysilicon are constructed.

Step (B) is illustrated in FIG. 2B. Various elements of FIG. 2B, such as2302, 2304, 2306, 2308 and 2310 have been described previously. Implantsare done to form source-drain regions 2312 and 2314 for both nMOS andpMOS transistors. A rapid thermal anneal (RTA) is then done to activatedopants. Alternatively, a spike anneal or a laser anneal could be done.

Step (C) is illustrated in FIG. 2C. Various elements of FIG. 2C such as2302, 2304, 2306, 2308, 2310, 2312 and 2314 have been describedpreviously. An oxide layer 2316 is deposited and planarized with CMP.

Step (D) is illustrated in FIG. 2D. Various elements of FIG. 2D such as2302, 2304, 2306, 2308, 2310, 2312, 2314, and 2316 have been describedpreviously. Hydrogen is implanted into the wafer at a certain depthindicated by 2318. Alternatively, helium can be implanted.

Step (E) is illustrated in FIG. 2E. Various elements of FIG. 2E such as2302, 2304, 2306, 2308, 2310, 2312, 2314, 2316, and 2318 have beendescribed previously. Using a temporary bonding adhesive, the oxidelayer is bonded to a temporary carrier wafer 2320. An example of atemporary bonding adhesive is a polyimide that can be removed by shininga laser. An example of a temporary carrier wafer is glass.

Step (F) is illustrated in FIG. 2F. The structure shown in FIG. 2E iscleaved at the hydrogen plane using a mechanical force. Alternatively,an anneal could be used. Following this cleave, a CMP is done toplanarize the surface. An oxide layer is then deposited. FIG. 2F showsthe structure after all these steps are done, with the deposited oxidelayer indicated as 2328. After the cleave, the p-Silicon region isindicated as 2322, the n− Silicon region is indicated as 2324, and theoxide isolation regions are indicated as 2326. Various other elements inFIG. 23F such as 2308, 2320, 2312, 2314, 2310, and 2316 have beendescribed previously.

Step (G) is illustrated in FIG. 2G. The structure shown in FIG. 2F isbonded to a glass substrate 2332 with an oxide layer 2330 usingoxide-to-oxide bonding. Various elements in FIG. 2G such as 2308, 2326,2322, 2324, 2312, 2314, and 2310 have been described previously. Oxideregions 2328 and 2330 are bonded together. The temporary carrier waferfrom FIG. 2F is removed by shining a laser through it. A ClVIP processis then conducted to reach the surface of the gate electrode 2308. Thus,the structure may be illustrated by FIG. 2H. The oxide layer remainingis denoted as 2334.

Step (H) is illustrated in FIG. 2I. Various elements in FIG. 2I such as2312, 2314, 2328, 2330, 2332, 2334, 2326, 2324, and 2322 have beendescribed previously. The dummy gate dielectric and dummy gate electrodeare etched away in this step and a replacement gate dielectric 2336 anda replacement gate electrode 2338 are deposited and planarized with CMP.Examples of replacement gate dielectrics could be hafnium oxide oraluminum oxide while examples of replacement gate electrodes could beTiN or TaN or some other material. Contact formation, metallization andother steps for building a display/microdisplay are then conducted. Itcan be observed that after attachment to the glass substrate, no processstep requires a processing temperature above 400° C.

FIGS. 3A-3F describe an embodiment of this invention, wheresingle-crystal Silicon junction-less transistors are constructed aboveglass substrates at a temperature approximately less than 400° C. Anion-cut process (which is a smart layer transfer process) is utilizedfor this purpose. This process could include several steps that occur ina sequence from Step (A) to Step (F). Many of these steps share commoncharacteristics, features, modes of operation, etc. When identicalreference numbers are used in different drawing figures, they are usedto indicate analogous, similar or identical structures to enhance theunderstanding of the present invention by clarifying the relationshipsbetween the structures and embodiments presented in the variousdiagrams—particularly in relating analogous, similar or identicalfunctionality to different physical structures.

Step (A) is illustrated in FIG. 3A. A glass substrate 2402 is taken anda layer of silicon oxide 2404 is deposited on the glass substrate 2402.Step (B) is illustrated in FIG. 3B. A p− Silicon wafer 2406 is implantedwith a n+ Silicon layer 2408 above which an oxide layer 2410 isdeposited. A RTA or spike anneal or laser anneal is conducted toactivate dopants. Following this, hydrogen is implanted into the waferat a certain depth indicated by 2412. Alternatively, helium can beimplanted.Step (C) is illustrated in FIG. 3C. The structure shown in FIG. 3B isflipped and bonded onto the structure shown in FIG. 3A usingoxide-to-oxide bonding. This bonded structure is cleaved at its hydrogenplane, after which a CMP is done. FIG. 3C shows the structure after allthese processes are completed. 2414 indicates the n+Si layer, while2402, 2404, and 2410 have been described previously.Step (D) is illustrated in FIG. 3D. A lithography and etch process isconducted to pattern the n+ Silicon layer 2414 in FIG. 3C to form n+Silicon regions 2418 in FIG. 3D. The glass substrate is indicated as2402 and the bonded oxide layers 2404 and 2410 are shown as well.Step (E) is illustrated in FIG. 3E. A gate dielectric 2420 and gateelectrode 2422 are deposited, following which a CMP is done. 2402 is asdescribed previously. The n+Si regions 2418 are not visible in thisfigure, since they are covered by the gate electrode 2422. Oxide regions2404 and 2410 have been described previously.Step (F) is illustrated in FIG. 3F. The gate dielectric 2420 and gateelectrode 2422 from FIG. 3E are patterned and etched to form thestructure shown in FIG. 3F. The gate dielectric after the etch processis indicated as 2424 while the gate electrode after the etch process isindicated as 2426. n+Si regions are indicated as 2418 while the glasssubstrate is indicated as 2402. Oxide regions 2404 and 2410 have beendescribed previously. It can be observed that a three-side gatedjunction-less transistor is formed at the end of the process describedwith respect of FIGS. 3A-3F. Contacts, metallization and other steps forconstructing a display/microdisplay are performed after the stepsindicated by FIGS. 3A-3F. It can be seen that the glass substrate is notexposed to temperatures greater than approximately 400° C. during anystep of the above process for forming the junction-less transistor.

FIGS. 4A-D describe an embodiment of this invention, where amorphous Sior polysilicon junction-less transistors are constructed above glasssubstrates at a temperature less than 400° C. This process could includeseveral steps that occur in a sequence from Step (A) to Step (D). Manyof these steps share common characteristics, features, modes ofoperation, etc. When identical reference numbers are used in differentdrawing figures, they are used to indicate analogous, similar oridentical structures to enhance the understanding of the presentinvention by clarifying the relationships between the structures andembodiments presented in the various diagrams—particularly in relatinganalogous, similar or identical functionality to different physicalstructures.

Step (A) is illustrated in FIG. 4A. A glass substrate 2502 is taken anda layer of silicon oxide 2504 is deposited on the glass substrate 2502.Following this deposition, a layer of n+Si 2506 is deposited usinglow-pressure chemical vapor deposition (LPCVD) or plasma enhancedchemical vapor deposition (PECVD). This layer of n+Si could optionallybe hydrogenated.Step (B) is illustrated in FIG. 4B. A lithography and etch process isconducted to pattern the n+ Silicon layer 2506 in FIG. 4A to form n+Silicon regions 2518 in FIG. 4B. 2502 and 2504 have been describedpreviously.Step (C) is illustrated in FIG. 4C. A gate dielectric 2520 and gateelectrode 2522 are deposited, following which a CMP is optionally done.2502 is as described previously. The n+Si regions 2518 are not visiblein this figure, since they are covered by the gate electrode 2522.Step (D) is illustrated in FIG. 4D. The gate dielectric 2520 and gateelectrode 2522 from FIG. 4C are patterned and etched to form thestructure shown in FIG. 4D. The gate dielectric after the etch processis indicated as 2524 while the gate electrode after the etch process isindicated as 2526. n+Si regions are indicated as 2518 while the glasssubstrate is indicated as 2502. It can be observed that a three-sidegated junction-less transistor is formed at the end of the processdescribed with respect of FIGS. 4A-4D. Contacts, metallization and othersteps for constructing a display/microdisplay are performed after thesteps indicated by FIGS. 4A-4D. It can be seen that the glass substrateis not exposed to temperatures greater than 400° C. during any step ofthe above process for forming the junction-less transistor.

FIGS. 5A-5C illustrate an embodiment of this invention, where amicrodisplay is constructed using stacked RGB LEDs and control circuitsare connected to each pixel with solder bumps. This process couldinclude several steps that occur in a sequence from Step (A) to Step(C). Many of these steps share common characteristics, features, modesof operation, etc. When identical reference numbers are used indifferent drawing figures, they are used to indicate analogous, similaror identical structures to enhance the understanding of the presentinvention by clarifying the relationships between the structures andembodiments presented in the various diagrams—particularly in relatinganalogous, similar or identical functionality to different physicalstructures.

Step (A) is illustrated in FIG. 5A. Using procedures similar to FIG.4A-4S of parent U.S. patent application Ser. No. 13/274,161 issued as9,197,804, incorporated herein by reference, the structure shown in FIG.5A is constructed. Various elements of FIG. 5A are as follows:

-   2646— a glass substrate,-   2644— an oxide layer, could be a conductive oxide such as ITO,-   2634— an oxide layer, could be a conductive oxide such as ITO-   2633— a an optional reflector, could be a Distributed Bragg    Reflector or some other type of reflector,-   2632— a P-type confinement layer that is used for a Blue LED (One    example of a material for this region is GaN),-   2630— a buffer layer that is typically used for a Blue LED (One    example of a material for this region is AlGaN),-   2628— a multiple quantum well used for a Blue LED (One example of    materials for this region are InGaN/GaN),-   2627— a N-type confinement layer that is used for a Blue LED (One    example of a material for this region is GaN).-   2648— an oxide layer, may be preferably a conductive metal oxide    such as ITO,-   2622— an oxide layer, may be preferably a conductive metal oxide    such as ITO,-   2621— an optional reflector (for example, a Distributed Bragg    Reflector),-   2620— a P-type confinement layer that is used for a Green LED (One    example of a material for this region is GaN),-   2618—a buffer layer that is typically used for a Green LED (One    example of a material for this region is AlGaN),-   2616—a multiple quantum well used for a Green LED (One example of    materials for this region are InGaN/GaN),-   2615—a N-type confinement layer that is used for a Green LED (One    example of a material for this region is GaN),-   2652—an oxide layer, may be preferably a conductive metal oxide such    as ITO,-   2610—an oxide layer, may be preferably a conductive metal oxide such    as ITO,-   2609—an optional reflector (for example, a Distributed Bragg    Reflector),-   2608—a P-type confinement layer used for a Red LED (One example of a    material for this region is AlInGaP),-   2606—a multiple quantum well used for a Red LED (One example of    materials for this region are AlInGaP/GaInP),-   2604—a P-type confinement layer used for a Red LED (One example of a    material for this region is AlInGaP),-   2656—an oxide layer, may be preferably a transparent conductive    metal oxide such as ITO, and-   2658—a reflector (for example, aluminum or silver).    Step (B) is illustrated in FIG. 5B. Via holes 2662 are etched to the    substrate layer 2646 to isolate different pixels in the    microdisplay/display. Also, via holes 2660 are etched to make    contacts to various layers of the stack. These via holes may be    preferably not filled. An alternative is to fill the via holes with    a compatible oxide and planarize the surface with CMP. Various    elements in FIG. 5B such as 2646, 2644, 2634, 2633, 2632, 2630,    2628, 2627, 2648, 2622, 2621, 2620, 2618, 2616, 2615, 2652, 2610,    2609, 2608, 2606, 2604, 2656 and 2658 have been described    previously.    Step (C) is illustrated in FIG. 5C. Using procedures similar to    those described in respect to FIGS. 4A-4S of parent U.S. patent    application Ser. No. 13/274,161 issued as 9,197,804, incorporated    herein by reference, the via holes 2660 have contacts 2664 (for    example, with Aluminum) made to them. Also, using procedures similar    to those described in FIGS. 4A-4S, nickel layers 2666, solder layers    2668, and a silicon sub-mount 2670 with circuits integrated on them    are constructed. The silicon sub-mount 2670 has transistors to    control each pixel in the microdisplay/display. Various elements in    FIG. 5C such as 2646, 2644, 2634, 2633, 2632, 2630, 2628, 2627,    2648, 2622, 2621, 2620, 2618, 2616, 2615, 2652, 2610, 2609, 2608,    2606, 2604, 2656, 2660, 2662, and 2658 have been described    previously. It can be seen that the structure shown in FIG. 5C can    have each pixel emit a certain color of light by tuning the voltage    given to the red, green and blue layers within each pixel. This    microdisplay may be constructed using the ion-cut technology, a    smart layer transfer technique.

FIGS. 6A-6D illustrate an embodiment of this invention, where amicrodisplay is constructed using stacked RGB LEDs and control circuitsare integrated with the RGB LED stack. This process could includeseveral steps that occur in a sequence from Step (A) to Step (D). Manyof these steps share common characteristics, features, modes ofoperation, etc. When identical reference numbers are used in differentdrawing figures, they are used to indicate analogous, similar oridentical structures to enhance the understanding of the presentinvention by clarifying the relationships between the structures andembodiments presented in the various diagrams—particularly in relatinganalogous, similar or identical functionality to different physicalstructures.

Step (A) is illustrated in FIG. 6A. Using procedures similar to thoseillustrated in FIGS. 4A-4S of parent U.S. patent application Ser. No.13/274,161 issued as 9,197,804, incorporated herein by reference, thestructure shown in FIG. 6A is constructed. Various elements of FIG. 6Aare as follows:

-   2746— a glass substrate,-   2744— an oxide layer, could be a conductive oxide such as ITO,-   2734— an oxide layer, could be a conductive oxide such as ITO,-   2733— a an optional reflector (e.g., a Distributed Bragg Reflector    or some other type of reflector),-   2732 —a P-type confinement layer that is used for a Blue LED (One    example of a material for this region is GaN),-   2730— a buffer layer that is typically used for a Blue LED (One    example of a material for this region is AlGaN),-   2728— a multiple quantum well used for a Blue LED (One example of    materials for this region are InGaN/GaN),-   2727— a N-type confinement layer that is used for a Blue LED (One    example of a material for this region is GaN),-   2748— an oxide layer, may be preferably a conductive metal oxide    such as ITO,-   2722 —an oxide layer, may be preferably a conductive metal oxide    such as ITO,-   2721 —an optional reflector (e.g., a Distributed Bragg Reflector),-   2720— a P-type confinement layer that is used for a Green LED (One    example of a material for this region is GaN),-   2718—a buffer layer that is typically used for a Green LED (One    example of a material for this region is AlGaN),-   2716—a multiple quantum well used for a Green LED (One example of    materials for this region are InGaN/GaN),-   2715—a N-type confinement layer that is used for a Green LED (One    example of a material for this region is GaN),-   2752—an oxide layer, may be preferably a conductive metal oxide such    as ITO,-   2710—an oxide layer, may be preferably a conductive metal oxide such    as ITO,-   2709—an optional reflector (e.g., a Distributed Bragg Reflector),-   2708—a P-type confinement layer used for a Red LED (One example of a    material for this region is AlInGaP),-   2706—a multiple quantum well used for a Red LED (One example of    materials for this region are AlInGaP/GaInP),-   2704—a P-type confinement layer used for a Red LED (One example of a    material for this region is AlInGaP),-   2756—an oxide layer, may be preferably a transparent conductive    metal oxide such as ITO,-   2758—a reflector (e.g., aluminum or silver).    Step (B) is illustrated in FIG. 6B. Via holes 2762 are etched to the    substrate layer 2746 to isolate different pixels in the    microdisplay/display. Also, via holes 2760 are etched to make    contacts to various layers of the stack. These via holes may be    preferably filled with a compatible oxide and the surface can be    planarized with CMP. Various elements of FIG. 6B such as 2746, 2744,    2734, 2733, 2732, 2730, 2728, 2727, 2748, 2722, 2721, 2720, 2718,    2716, 2715, 2752, 2710, 2709, 2708, 2706, 2704, 2756 and 2758 have    been described previously.    Step (C) is illustrated in FIG. 6C. Metal 2764 (for example) is    constructed within the via holes 2760 using procedures similar to    those described in respect to FIGS. 4A-4S of parent U.S. patent    application Ser. No. 13/274,161 issued as 9,197,804, incorporated    herein by reference. Following this construction, an oxide layer    2766 is deposited. Various elements of FIG. 6C such as 2746, 2744,    2734, 2733, 2732, 2730, 2728, 2727, 2748, 2722, 2721, 2720, 2718,    2716, 2715, 2752, 2710, 2709, 2708, 2706, 2704, 2756, 2760, 2762 and    2758 have been described previously.

Step (D) is illustrated in FIG. 6D. Using procedures described inco-pending U.S. patent application Ser. No. 12/901,890, issued as U.S.Pat. No. 8,026,521, the entire contents of which is incorporated hereinby reference, a single crystal silicon transistor layer 2768 can bemonolithically integrated using ion-cut technology atop the structureshown in FIG. 6C. This transistor layer 2768 is connected to variouscontacts of the stacked LED layers (not shown in the figure forsimplicity). Following this connection, nickel layer 2770 is constructedand solder layer 2772 is constructed. The packaging process then isconducted where the structure shown in FIG. 6D is connected to a siliconsub-mount. It can be seen that the structure shown in FIG. 6D can haveeach pixel emit a certain color of light by tuning the voltage given tothe red, green and blue layers within each pixel. This microdisplay isconstructed using the ion-cut technology, a smart layer transfertechnique.

The embodiments of this invention described in FIGS. 5-6 may enablenovel implementations of “smart-lighting concepts” (also known asvisible light communications) that are described in “Switching LEDs onand off to enlighten wireless communications”, EETimes, June 2010 by R.Colin Johnson. For these prior art smart lighting concepts, LED lightscould be turned on and off faster than the eye can react, so signalingor communication of information with these LED lights is possible. Anembodiment of this invention involves designing thedisplays/microdisplays described in FIGS. 5-6 to transmit information,by modulating wavelength of each pixel and frequency of switching eachpixel on or off. One could thus transmit a high bandwidth through thevisible light communication link compared to a LED, since each pixelcould emit its own information stream, compared to just one informationstream for a standard LED. The stacked RGB LED embodiment described inFIGS. 4A-4S of parent U.S. patent application Ser. No. 13/274,161 issuedas 9,197,804, incorporated herein by reference, could also provide animproved smart-light than prior art since it allows wavelengthtunability besides the ability to turn the LED on and off faster thanthe eye can react.

Optical Interconnects:

Optical interconnects in inter-chip communication have become a feasiblereplacement for electrical interconnects as the line capacitance of thelatter has imposed increasingly difficult limitations due to scaling. Aselectrical component density increases, optical lines can carry moreinformation between electrical components.

An optical interconnect system may consist of several components. Thefirst is a transmission component that generates and modulates the lightthat is used to send the information. The second is a network ofwaveguides that guides the light to the receiving destination on thechip. Finally, there is the receiver network, which converts the lightback to electrical signals so that the information can be processed bythe electronic devices on the chip.

The transmission component is typically built out of lasers andmodulators. Lasers are built typically using III-V semiconductors likeGaAs, InP, and InGaAs which have superior optical mechanisms compared toGroup IV semiconductors such as silicon or germanium. The drawback withthese III-V materials is that their processing is not compatible withthe Group IV materials used for the electronic components of the chip.In this case, it may be advantageous that the laser is placed off-chip,which additionally offers the advantage of insulating the laseroperation from the temperature variations and power limits of the chipitself. Another option is to use a layer of LEDs in a monolithic 3Dconfiguration as the light sources for the data transmission. Theadvantage of this option is that LEDs are cheaper than lasers and areeasier to modulate directly. However, LEDs present some limitations asto the data transmission efficiency through the waveguides since, unlikethe generated light from lasers, the generated light from LEDs are notcoherent or collimated, and, hence, waveguide loss is significant.

Waveguides are passive optical components designed to confine light inone direction. Typically they are made out of Silicon, Silicon Dioxide,and Silicon Nitride, which are materials already being used for theelectronic components in conventional chips, and thus are materiallycompatible and can be grown or deposited on top of these layers. So inSilicon-based chips, such dielectric waveguides are usually used, inwhich a material with high permittivity corresponding to a high index ofrefraction, is surrounded by a material with lower permittivitycorresponding to a lower index of refraction. The structure then guidesoptical waves by total internal reflection. For example, Silicon may beused for the high permittivity material and Silicon dioxide for the lowpermittivity material. Another type of waveguides use photonic crystalstructures, which again can be constructed using Silicon and Silicondioxide. In most cases, masks and etching are used to construct thestructures. One of the potential disadvantages of dielectric waveguidesis they are not able to contain light where sharp turns are requiredbecause of the limits imposed on light refraction between two materialsby the critical angle, and light leakage may result. So they may besuitable for chip-to-chip optical communications where most waveguidesonly need to be mostly straight and here the significant distancebetween the two chips may allow for gradual turns if needed.

Yet another type of waveguides is called hollow metal waveguides (HMWG),made of trenches in the material with walls coated with reflectivemetals which may include, for example, silver. In combination withbeam-splitters, HMWG's allow light to be reflected around sharp corners,which may be a potential advantage as described in Mathai, S., et al.,US Patent Application 2009/0244716A1. In intra-chip opticalcommunications, where waveguide layer thickness may be limited, HMWG'smay be used to enable the sharp turns required for the light signals.

The receiving component may include an array of photodetectors,typically made from Ge or SiGe. These photodetectors may have a p-n orp-i-n structure and may be biased to capture photons and subsequentlyconvert them into electronic carriers.

Layer transfer technology may be utilized for constructing the layersfor an optical interconnect system.

LED-driven chip-to-chip optical interconnect:

The transmission component may consist of a layer of light-emittingdiodes (LEDs) physically coupled with a layer of control circuits tomanage the triggering of the LEDs so as to control the light beingtransmitted to enable data communication. The light may then be sentthrough a layer of waveguides which may distribute the light to theirrespective destinations on the chip, which may then be received by alayer of photo-detectors and converted to electrical signals by thereadout circuits that can be handled by the electronic components of thechip.

FIGS. 7A-7H illustrate an embodiment of the invention, where thetransmitter block: LED control circuit layer 3142, LED layer 3148;communication channel: waveguide layer 3136; and receiver block:photo-detector layer 3110, and readout circuit layer 3100 may be stackedmonolithically with layer transfer.

The process of forming the optical communication system may includeseveral steps that occur in a sequence from Step A to Step H. Many ofthese steps share common characteristics, features, modes of operation,etc. When identical reference numbers are used in different drawingfigures, they are used to indicate analogous, similar or identicalstructures to enhance the understanding of the present invention byclarifying the relationships between the structures and embodimentspresented in the various diagrams—particularly in relating analogous,similar or identical functionality to different physical structures.

Step (A): FIG. 7A illustrates the first step for constructing thephoto-detector layer 3110 and readout circuit layer 3100, where thephoto-detector layer 3110 may be formed atop the readout circuit layer3100 using layer transfer. FIG. 7A illustrates a cross-sectional view ofsilicon wafer substrate with pre-processed read-out circuits 3102, abovewhich an oxide layer 3104 may be deposited. Thus readout circuit layer3100 is formed. FIG. 7A further illustrates the cross-sectional view ofanother Silicon wafer 3112 which may have a p+ Silicon layer 3114, a pSilicon layer 3116, a n Silicon layer 3118, a n+ Silicon layer 3120, andan oxide layer 3122. These layers may be formed using procedures similarto those described in FIG. 15A-15G of incorporated parent U.S. Pat. No.9,197,804. An anneal may then be performed to activate dopants invarious layers. Hydrogen may be implanted in the wafer at a certaindepth depicted by dashed line 3190.

Step (B): FIG. 7B illustrates the photo-detector and readout circuitstructure 3192 formed by an ion-cut layer transfer process. Thephoto-detector layer 3110 of p+ pnn+ silicon consisting of thephoto-detector diodes may be layer transferred atop the silicon waferwith readout circuit layer 3100 wherein oxide layer 3104 may be bondedto oxide layer 3122, and p+ silicon layer 3115 may be a result of thecleave and polish operations. Procedures for layer transfer andalignment for forming the structure in FIG. 31B are similar toprocedures used for constructing the image sensor shown in FIGS. 15A-15Gof incorporated parent U.S. Pat. No. 9,197,804.

Step (C) is illustrated in FIG. 7C. An oxide layer 3124 may be depositedon top of p+ silicon layer 3115. Connections may be made to theterminals of the photo-detector by lithographic, etch, and filloperations similar to those described in FIGS. 15A-15G of incorporatedparent U.S. Pat. No. 9,197,804, and are indicated as p+ contact 3126 andn+ contact 3128. Various elements of FIG. 7C such as 3102, 3104, 3115,3116, 3118, 3120, and 3122 have been described previously herein or inincorporated parent U.S. Pat. No. 9,197,804. Contacts 3130 andinterconnects (not shown) for connecting terminals of thephoto-detector, such as p+ contact 3124 and p+ contact 3128, to read-outcircuits in silicon wafer substrate with pre-processed read-out circuits3102 may be done. Thus silicon wafer containing the photo-detectors andread-out circuits 3131 may be formed. The functionality of thephoto-detectors may be tested at this point.

As described previously, FIGS. 15A-15G of incorporated parent U.S. Pat.No. 9,197,804 illustrate a process whereby oxide vias constructed beforelayer transfer may be used to look through photo-detector layers toobserve alignment marks on the read-out circuit wafer below it. However,an alternative embodiment of this invention may involve constructingoxide vias after layer transfer. Essentially, after layer transfer ofstructures without oxide vias, oxide vias whose diameters are largerthan the maximum misalignment of the bonding/alignment scheme may beformed. This order of sequences may enable observation of alignmentmarks on the bottom read-out circuit wafer by looking through thephoto-detector wafer.

Waveguides are structures designed to confine light in one direction. InSilicon-based chips, dielectric waveguides are usually used, in which amaterial with high permittivity corresponding to a high index ofrefraction, is surrounded by a material with lower permittivitycorresponding to a lower index of refraction. The structure then guidesoptical waves by total internal reflection. For Silicon-based chips,convenient materials are Silicon for the high permittivity material andSilicon dioxide for the low permittivity material. Another type ofwaveguides use photonic crystal structures, which again can beconstructed using Silicon and Silicon dioxide. In most cases, masks andetching are used to construct the structures. Yet another type ofwaveguides may be called hollow metal waveguides (HMWG), made oftrenches in the material with walls coated with reflective metals whichmay include silver. In combination with beam-splitters, HMWG's allowlight to be reflected around sharp corners, which may be a potentialadvantage.

Step (D) is illustrated in FIG. 7D. Silicon waveguides 3136 may beformed on the SOI wafer 3132 and BOX 3134 by electron beam lithographyfollowed by electron cyclotron resonance plasma etching. The wafer maythen be coated with Silicon Dioxide 3138 to form the over-cladding. Itwill be obvious to one skilled in the art that many configurations andmaterial combinations are being currently used and/or possible in theformation of the waveguides. This invention is not limited to oneparticular configuration or set of materials. Hydrogen may be implantedin the wafer at a certain depth depicted by 3140. Thus, Silicon/SiliconDioxide waveguide layer 3139 may be formed.

Step (E) is illustrated in FIG. 7E. The Silicon/Silicon Dioxidewaveguide layer 3139 may then be ion-cut layer transferred atop thesilicon wafer containing the photo-detectors and read-out circuits 3131.Procedures for layer transfer and alignment for forming the structure3141 in FIG. 7E are similar to procedures used previously herein and/orin incorporated parent U.S. Pat. No. 9,197,804: Silicon/Silicon Dioxidewaveguide layer 3139 may be flipped and bonded atop silicon wafercontaining the photo-detectors and read-out circuits 3131 usingoxide-oxide bonding and the Silicon substrate 3132 may then be cleavedand polished until the oxide layer 3134, now labeled 3135 after thecleave and polish process, is reached.

Step (F) is shown in FIG. 7F which is used for constructing the LED andcontrol circuit layers, where the Red LED layer from Red LED wafer 3148may be formed atop the electronic control circuit layer 3142 usingion-cut layer transfer. Silicon wafer with control circuits 3144 may beconventionally constructed, above which an oxide layer 3146 may bedeposited. Red LED wafer 3148 may include GaAs wafer 3150, n-typeconfinement layer 3152, multiple quantum well (MQW) layer 3154, P-typeconfinement layer 3156, and an ITO current spreader layer 3158. Examplesof materials used to construct these layers may include, but are notlimited to; doped AlInGaP for the n-type confinement layer 3152 andp-type confinement layer 3156, multiple quantum well layer 3154 could becomposed of AlInGaP and GaInP. These layers may be formed by processessuch as molecular beam epitaxy, MOCVD, etc. The red LED wafer describedin FIG. 7F may have hydrogen implanted into it at a certain depth asshown by dotted line 3160. Alternatively, helium can be implanted.

Step (G) is shown in FIG. 7G. The layer of GaAs structures consisting ofthe red LEDs 3148 may be layer transferred atop the silicon wafer withthe control circuits 3142 forming the LED stack 3170. Procedures forlayer transfer and alignment for forming the structure in FIG. 7G may besimilar to procedures used for constructing the LED lighting shown inFIGS. 12A-12F of incorporated parent U.S. Pat. No. 9,197,804. n-GaAslayer 3152 is renamed 3153 after the cleaving and polishing process. AnITO layer 3162 is deposited atop n-GaAs layer 3153, thus forming the LEDstack 3170. The functionality of the LEDs may be tested at this point.

Step (H) is illustrated by FIG. 7H. The structure shown in FIG. 31G, LEDstack 3170, may be flipped and bonded atop the structure shown in FIG.7E, structure 3141, using oxide-to-oxide bonding of ITO layer 3162 andoxide layer 3135. Various elements in FIG. 7H such as 3102, 3104, 3115,3116, 3118, 3120, 3122, 3124, 3135, 3136, 3138, 3144, 3146, 3153, 3154,3156, 3158 and 3162 have been described previously herein and/or inincorporated parent U.S. Pat. No. 9,197,804. Thus, LED-drivenchip-to-chip optical interconnect 3199 may be formed.

Laser-driven chip-to-chip optical interconnect:

FIGS. 8A-8D illustrate an embodiment of this invention, where thetransmitter block: modulator control circuit layer 3242, modulator layer3248; communication channel: waveguide layer 3236; and receiver block:photodetector layer 3210, and readout circuit layer 3200 are stackedmonolithically with layer transfer.

Step (A): FIG. 8A illustrates the first step for constructing thewaveguide layer 3236, photodetector layer 3210, readout circuit layer3200, where the waveguide layer 3236 with oxide layer 3234, oxide layer3228, oxide layer 3221 oxide layer 3222 and oxide layer 3204 may beformed atop the photodetector layer 3210, which in turn may be formedatop the readout circuit layer 3200 using layer transfer proceduresdescribed in FIG. 7A-7E.

Step (B) is shown in FIG. 8B which is used for constructing themodulator and control circuit layers, where the modulator layer isformed atop the electronic control circuit layer using layer transfer.3242 shows a cross-sectional view of 3244, a silicon wafer with controlcircuits constructed on it, above which an oxide layer 3246 isdeposited. 3248 shows the cross-sectional view of a Silicon wafer 3250containing Silicon-Germanium modulators and may include a P-typeSilicon-Germanium buffer layer 3252, an undoped Silicon-Germanium spacer3254, a Germanium/Silicon-Germanium multiple quantum well (MQW) 3256,another undoped Silicon-Germanium spacer 3258, an N-typeSilicon-Germanium layer 3260, and a deposited oxide layer 3262. Examplesof materials used to construct these layers, include, but are notlimited to, doped GaAs for the N-type cap layer 3260 and P-type bufferlayer 3252, the multiple quantum well layer 3256 could be of GaAs andAlGaAs. A double heterostructure configuration or single quantum wellconfiguration could be used instead of a multiple quantum wellconfiguration. Various other material types and configurations could beused for constructing the modulators for this process. The modulatorwafer described in FIG. 8B has hydrogen implanted into it at a certaindepth. The dotted line 3264 depicts the hydrogen implant. Alternatively,helium can be implanted.

Step (C) is shown in FIG. 8C. The layer of SiGe structures consisting ofthe modulators 3248 is layer transferred atop the silicon wafer with thecontrol circuits 3242. Procedures for layer transfer and alignment forforming the structure in FIG. 8C are similar to procedures used forconstructing the photo-detectors shown in FIGS. 15A-G of incorporatedparent U.S. Pat. No. 9,197,804. The functionality of the modulators canbe tested at this point.

Step (D) is illustrated by FIG. 8D. The structure shown in FIG. 8C isflipped and bonded atop the structure shown in FIG. 8A usingoxide-to-oxide bonding of layers 3266 and 3234. Various elements in FIG.32D such as 3202, 3204, 3214, 3216, 3218, 3220, 3222, 3234, 3236, 3238,3244, 3246, 3252, 3254, 3256, 3258, 3260, 3262 and 3266 have beendescribed previously herein and/or within incorporated parent U.S. Pat.No. 9,197,804. An external laser 3268 (typically made of InP) is thencoupled to the structure via an optical fiber 3270 by known techniques.

On-Chip LED-Driven Optical Interconnects

FIGS. 9A-9C illustrate an embodiment of this invention, where theLED-driven optical communication is among sections on a single chip.

FIG. 9A illustrates a cross-sectional view of a transmitter section 3350and a receiver section 3360. The transmitter section 3350 may includeLED control circuit layer 3352, LED layer 3354 and waveguide layer 3356stacked monolithically with layer transfer. The receiver section 3360may contain readout circuit layer 3362, photo-detector layer 3364 andwaveguide layer 3166 stacked monolithically with layer transfer. Layertransfer procedures are similar to those described in FIGS. 7A-7Hherein.

FIG. 9B illustrates an exemplary top view of integrated circuit chip3310 which may include integrated circuits 3312, optical transmittersusing LEDs 3314 and 3316, optical receivers using photo-detectors 3318and 3320, and waveguide sections 3322 and 3324 enabling opticalcommunication from one end of the chip to the other.

FIG. 9C illustrates a cross-sectional view (not to scale) of anintegrated circuit chip 3330 with a substrate 3332, control and readoutcircuit sections 3338 and 3340, integrated circuit section 3334, LED andphoto-detector layer 3336, and waveguide layer 3342. Persons of ordinaryskill in the art will appreciate that each layer may use the samematerial throughout the layer for ease of processing, but may differamong different layers. As an example, the waveguide layer 3342 may useSilicon, the LED and photo-detector layer 3336 may use III-Vsemiconductor material, the layer with control and readout circuitsections 3338 and 3340 and integrated circuits section 3334 may useSilicon, and the substrate 3332 may use silicon.

FIG. 10 illustrates cross-sectional view of a waveguide structure 3470with Hollow-metal waveguide (HMWG) 3472, beam-splitters 3474 and 3476and light signal 3478. HMWG with reflective metal coating andbeam-splitters are capable of guiding light through sharp turns byallowing sharp-angled reflections which may be a potential advantagecompared to dielectric waveguides when waveguide layer thickness is inconsideration.

On-Chip Laser-Driven Optical Interconnects

FIGS. 11A-11C illustrate an embodiment of this invention, where thelaser-driven optical communication is among sections on a single chip.

FIG. 11A illustrates a cross-sectional view of a transmitter section3550 and a receiver section 3560. The transmitter section 3550 mayinclude modulator control circuit layer 3552, modulator layer 3554 andwaveguide layer 3556 stacked monolithically with layer transfer,external laser 3558, fiber-optic coupling 3559 (connecting externallaser 3559 to modulator layer 3554). The receiver section 3560 maycontain a readout circuit layer 3562, photo-detector layer 3564 andwaveguide layer 3566 stacked monolithically with layer transfer. Layertransfer procedures are similar to those described in FIG. 8A-8D herein.

FIG. 11B illustrates an exemplary top view of integrated circuit chip3510 which may include integrated circuits 3512, optical transmittersusing external laser 3526, fiber-optic couplings 3528 and 3529,modulators 3514 and 3516, optical receivers using photo-detectors 3518and 3520, and waveguide sections 3522 and 3524 enabling opticalcommunication from one end of the chip to the other.

FIG. 11C illustrates a cross-sectional view (not to scale) of anintegrated circuit chip 3530 with substrate 3532, control and readoutcircuit sections 3538 and 3540, integrated circuit section 3534,modulator and photo-detector layer 3536, waveguide layer 3542, externallaser 3544 and fiber-optic coupling 3546. Persons of ordinary skill inthe art will appreciate that each layer may use the same materialthroughout the layer for ease of processing, but may differ amongdifferent layers. As an example, the waveguide layer 3542 may useSilicon, the modulator and photo-detector layer 3536 may use III-Vsemiconductor material, the layer with control and readout circuitsections 3538 and 3540 and integrated circuits section 3534 may useSilicon, and the substrate 3532 may use silicon.

As described in FIG. 10 , the waveguide layer may use HMWGs withreflective metal coating and beam-splitters capable of guiding lightthrough sharp turns by allowing sharp-angled reflections which may be apotential advantage compared to dielectric waveguides when waveguidelayer thickness is in consideration.

Persons of ordinary skill in the art will appreciate that while Siliconhas been suggested as the material for the photo-detector layer of FIG.7A, Germanium or Silicon-Germanium could be utilized. The advantage ofGermanium is that it is sensitive to infra-red wavelengths as well.However, Germanium also suffers from high dark current. Moreover, thephoto-detector layer 3110 is denoted as a p-n junction layer; however,any type of photo-detector layer, such as a p-i-n layer or some othertype of photo-detector can be used. Furthermore, the thickness of thephoto-detector layer may be typically less than approximately 5 μm, butmay also be greater. Moreover, a double hetero-structure configurationor single quantum well configuration could be used instead of a multiplequantum well configuration such as the shown multiple quantum well layer3154. Further, various other material types and configurations, such asGaAs, AlInGaP, and GaInP, could be used for constructing the red LEDsfor this process. Thus the invention is to be limited only by theappended claims.

Several material systems have been illustrated as examples for variousembodiments of this invention in this patent application. It will beclear to one skilled in the art based on the present disclosure thatvarious other material systems and configurations can also be usedwithout violating the concepts described. It will also be appreciated bypersons of ordinary skill in the art that the present invention is notlimited to what has been particularly shown and described hereinabove.Rather, the scope of the invention includes both combinations andsub-combinations of the various features described herein above as wellas modifications and variations which would occur to such skilledpersons upon reading the foregoing description. Thus the invention is tobe limited only by the appended claims.

We claim:
 1. A multi-level semiconductor device, the device comprising:a first level comprising integrated circuits; a second level comprisinga structure designed to conduct electromagnetic waves, wherein saidsecond level is disposed above said first level, wherein said integratedcircuits comprise single crystal transistors; and an oxide layerdisposed between said first level and said second level, wherein saidintegrated circuits comprise at least one processor, wherein said secondlevel is bonded to said oxide layer, and wherein said bonded comprisesoxide to oxide bonds.
 2. The device according to claim 1, wherein saidstructure is designed to conduct said electromagnetic waves in aconfined manner.
 3. The device according to claim 1, wherein saidstructure comprises an electromagnetic waveguide.
 4. The deviceaccording to claim 1, further comprising: a third level comprising acrystalline silicon layer, wherein a thickness of said crystallinesilicon layer is less than 60 microns.
 5. The device according to claim1, wherein said device comprises a crystalline III-V material.
 6. Thedevice according to claim 1, further comprising: a transmitter disposedwithin said second level, wherein said transmitter comprises at leastone modulator.
 7. The device according to claim 1, further comprising: athird level, wherein said third level comprises a layer comprisingelectronic circuits.
 8. A multi-level semiconductor device, the devicecomprising: a first level comprising a structure designed to conductelectromagnetic waves; a second level comprising integrated circuits,wherein said second level is disposed above said first level, whereinsaid integrated circuits comprise single crystal transistors; and anoxide layer disposed between said first level and said second level,wherein said integrated circuits comprise at least one processor,wherein said second level is bonded to said oxide layer, and whereinsaid bonded comprises oxide to oxide bonds.
 9. The device according toclaim 8, wherein said structure is designed to conduct saidelectromagnetic waves in a confined manner.
 10. The device according toclaim 8, wherein said structure comprises an electromagnetic waveguide.11. The device according to claim 8, further comprising: a third levelcomprising a crystalline silicon layer, wherein a thickness of saidcrystalline silicon layer is less than 60 microns.
 12. The deviceaccording to claim 8, wherein said device comprises a crystalline III-Vmaterial.
 13. The device according to claim 8, further comprising: atransmitter disposed within said second level, wherein said transmittercomprises at least one modulator.
 14. The device according to claim 8,further comprising: a third level, wherein said third level comprises alayer comprising electronic circuits.
 15. A multi-level semiconductordevice, the device comprising: a first level comprising integratedcircuits and communication control circuits; a second level comprising aplurality of interconnect lines, wherein said second level is disposedabove said first level, wherein said first level comprises a crystallinematerial; and an oxide layer disposed between said first level and saidsecond level, wherein said second level is bonded to said first level,wherein said bonded comprises oxide to oxide bonds; and at least oneelectromagnetic wave transmitter.
 16. The device according to claim 15,wherein said plurality of interconnect lines are designed to conductelectromagnetic waves in a confined manner.
 17. The device according toclaim 15, further comprising: a third level comprising a crystallinesilicon layer, wherein a thickness of said crystalline silicon layer isless than 60 microns.
 18. The device according to claim 15, wherein saiddevice comprises a crystalline III-V material.
 19. The device accordingto claim 15, further comprising: a transmitter circuit disposed withinsaid second level, wherein said transmitter circuit comprises at leastone modulator.
 20. The device according to claim 15, further comprising:a third level, wherein said third level comprises a layer comprisingelectronic circuits.